World of FPGA Podcast

Epizodes

• 
  WFP035 – FPGA Talk #2 Design Approaches 31.03.2026 49min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP035 – FPGA Talk #2 Design Approaches @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 35 of the World of FPGA Podcast. Talking about Design Approaches between Glenn and David. Welcome to the FPGA Talk #2 with the co-host Glenn Kirilow Content of this Episode Our journeys Pros and cons on different approaches Using AI and LLM Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP035 – FPGA Talk #2 Design Approaches appeared first on World of FPGA by David Kirchner.
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  WFP034 – FPGA High-Speed I/Os 17.03.2026 9min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP034 – FPGA High-Speed I/Os @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 34 of the World of FPGA Podcast. When sending or receiving faster signals by an FPGA, we need an appropriate logic behind this. And also fast I/Os are important. Content of this Episode Highspeed connections Some tricks about high speed on normal I/Os Especially the shift registers FPGA Conference 2026 Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP034 – FPGA High-Speed I/Os appeared first on World of FPGA by David Kirchner.
• 
  WFP033 – FPGA I/Os 14.10.2025 16min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP033 – FPGA I/Os @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 33 of the World of FPGA Podcast. Signals have to get into the FPGA and out of the FPGA. Here we need input/output pins. Here we will have a closer look. Content of this Episode I/O pad Logic block I/O standards Single-Ended Standards Differential Standards Key Considerations for I/O Standards Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP033 – FPGA I/Os appeared first on World of FPGA by David Kirchner.
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  WFP032 – FPGA Routing 30.09.2025 17min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP032 – FPGA Routing @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 32 of the World of FPGA Podcast. We have an internal digital highway inside an FPGA to connect all the different blocks. This highway has a lot of interesting features. Content of this Episode Routing Resources Connection lines Connection boxes Switching boxes But it depends Routing process Routing Algorithms Routing key challenges Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP032 – FPGA Routing appeared first on World of FPGA by David Kirchner.
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  WFP031 – FPGA Memory 16.09.2025 11min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP031 – FPGA Memory @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 31 of the World of FPGA Podcast. Memory is essential for a lot of things in your FPGA design. And FPGAs have a lot of different memory. Content of this Episode Flip-Flops SRAM blocks Ultra RAM Flash Memory High Bandwidth Memory Memory-Controller External Memory Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP031 – FPGA Memory appeared first on World of FPGA by David Kirchner.
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  WFP030 – FPGA Conference 2025 22.07.2025 35min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP030 – FPGA Conference 2025 @keyframes av_boxShadowEffect_av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 30 of the World of FPGA Podcast. It was time for a little trip again. I went to Munich to the three-day FPGA conference of PLC2 and the Vogel Verlag. Content of this Episode 3 day FPGA Conference in Munich FPGA Conference the biggest event in Europe Some facts 3 days 430 Participants 128 Lectures 110 Speakers 39 Exhibitors This year triple anniversary 40 years FPGA 30 years PLC2 10 years FPGA Conference All my visited talks Welcome to the Post-European Cyber Resilience Act (CRA) Era FPGAs and the Cyber Resilience Act Cyber Resilience Act: Planning your Security Future Making Simple FPGA Testbenches – Utilising Important Quality Measures A Cuckoo Hash-Based CAM Architecture for FPGA and ASIC Implementations Elevate your Design: Security and Power Efficiency with AMD Spartan UltraScale+ FPGAs Faster Change of Probe Signals using the Vivado Logic Analyzer Warning! Your FPGAs & SoC FPGAs are Under Attack Functional Safety for Hardware and Software Security, Regulations and FPGA-Based Systems – How to Make Your System Secure Verify the Bits that Fly : A Demonstration of Bitstream to HDL Equivalence Checking Why VUnit? Managing and Versioning Gateware Source Code on Git with Hog A Baseboard Management Controller for FPGA/SoC Board Supervision and Faster Bringup GateMate FPGA: Qualification for Radiation-Tolerant Applications GateMate FPGA: High-Speed Transceiver (SerDes) Hands-On Project-Based and Non-Project-Based Scripting in Vivado Multi-Run Management Using Vivado How to Drive Parallel High-Speed Circuits from an AMD FPGA Next FPGA conference is from 30 June – 2 July 2026 Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP030 – FPGA Conference 2025 appeared first on World of FPGA by David Kirchner.
• 
  WFP029 – FPGA DSP 17.06.2025 8min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP029 – FPGA DSP @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 29 of the World of FPGA Podcast. How can FPGAs calculate so fast? The secret inside an FPGA is a digital signal processing block. Content of this Episode What does DSP stand for? Common parts inside an DSP block Function representation Important facts Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP029 – FPGA DSP appeared first on World of FPGA by David Kirchner.
• 
  WFP028 – FPGA Talk #1 FPGA companies 03.06.2025 27min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP028 – FPGA Talk #1 FPGA companies @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 28 of the World of FPGA Podcast. Talking about our favorite FPGA companies. Welcome to the FPGA Talk with the new co-host Glenn Kirilow Content of this Episode Feedback FPGA companies AMD or XILINX Lattice Altera Cologne Chip GoWin Atmel, Microsemi and Microchip Use other FPGAs in future Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP028 – FPGA Talk #1 FPGA companies appeared first on World of FPGA by David Kirchner.
• 
  WFP027 – FPGA Slices 13.05.2025 6min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP027 – FPGA Slices @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 27 of the World of FPGA Podcast. We will dive deep into the FPGA architecture. This episode is about slices. Content of this Episode What are slices? Difference between FPGA manufacturer Configuration Housekeeping Links to older episodes WFP005 – Inside FPGA – basics WFP006 – Inside FPGA – specialties Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP027 – FPGA Slices appeared first on World of FPGA by David Kirchner.
• 
  WFP026 – FPGA Talk Intro 29.04.2025 36min

  .avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP026 – FPGA Talk Intro @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 26 of the World of FPGA Podcast. About the hosts. Who are we, what do we do and our FPGA journey. Welcome to the FPGA Talk with the new co-host Glenn Kirilow Content of this Episode Introduction Glenn Introduction David Contact between Glenn and David First FPGA projects Way to VHDL PCB Software Time distribution at work Issue on Spartan 3 Issue on Zynq Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP026 – FPGA Talk Intro appeared first on World of FPGA by David Kirchner.
• 
  WFP025 – FPGA Implementation 15.04.2025 5min

  Have you ever asked yourself, what happens during FPGA implementation? In this episode I try to give an answer. Content of this Episode: * Placement * Routing * After routing process * Similarity to a PCB layout And for now come into our Newsletter and also follow us on LinkedIn. The post WFP025 – FPGA Implementation appeared first on World of FPGA by David Kirchner.
• 
  WFP024 – FPGA Synthesis 25.03.2025 5min

  Have you ever asked yourself, what happens during FPGA synthesis? In this episode I try to give an answer. Content of this Episode: * What is a netlist? * Synthesis tool * Elaboration Substep * Matching to technology And for now come into our Newsletter and also follow us on LinkedIn. The post WFP024 – FPGA Synthesis appeared first on World of FPGA by David Kirchner.
• 
  WFP023 – FPGA Development Process 04.03.2025 6min

  FPGA development is a lot of fun. But also think about an appropriate development process. Content of this Episode: * Electronics development process * Validation vs. Verification * Difference to the FPGA development process And for now come into our Newsletter and also follow us on LinkedIn. The post WFP023 – FPGA Development Process appeared first on World of FPGA by David Kirchner.
• 
  WFP022 – VHDL Testbench 11.02.2025 9min

  VHDL Testbenches have many interesting features to simulate and test your VHDL module. Let’s have a look into these functions. Content of this Episode: * VHDL Testbenches * Using data files * Multiple modules * Automatic tests * More automation And for now come into our Newsletter and also follow us on LinkedIn. The post WFP022 – VHDL Testbench appeared first on World of FPGA by David Kirchner.
• 
  WFP021 – 2024 Review and Outlook 28.01.2025 9min

  We are looking back on 2024 and then we try an outlook into 2025. Content of this Episode: * Welcome in 2024 * Welcome back in this podcast :) * Review of 2024 * some private facts * Business * Outlook into 2025 * Business * Private things And for now come into our Newsletter and also follow us on LinkedIn. The post WFP021 – 2024 Review and Outlook appeared first on World of FPGA by David Kirchner.
• 
  WFP020 – Simulation 30.01.2024 16min

  Let us talk about simulations and their benefits for your FPGA development projects. Content of this Episode: * Simulations in general * Simulations in FPGA development * Benefits for your FPGA development projects * How to start with simulations * What are the boundaries of simulation * Simulate a hole design or only modules And for now come into our Newsletter and also follow us on LinkedIn. The post WFP020 – Simulation appeared first on World of FPGA by David Kirchner.
• 
  WFP019 – 2023 Review and Outlook 16.01.2024 8min

  We are looking back on 2023 and then we try an outlook into 2024. Content of this Episode: * Happy New Year and all the best for 2024 * Review of 2023 * some private facts * Business * Outlook into 2024 * Business * Private things * Next webinar in February 2024 And for now come into our Newsletter and also follow us on LinkedIn. The post WFP019 – 2023 Review and Outlook appeared first on World of FPGA by David Kirchner.
• 
  WFP018 – Debugging an ARM 29.08.2023 12min

  In addition to the last episode we will now have a look into the process of debugging an ARM core software. Content of this Episode: * Debugging an ARM (in a SoC) * Use UART and printf * Debug your bare metal application in Vitis * Debug your Linux application in Vitis And for now come into our Newsletter and also follow us on LinkedIn. The post WFP018 – Debugging an ARM appeared first on World of FPGA by David Kirchner.
• 
  WFP017 – Debugging an FPGA 15.08.2023 13min

  Let’s dive deeper into the debugging stuff. There are different ways of debugging an FPGA and the logic inside. Content of this Episode: * Debugging an FPGA * Observe signal outputs * Bring some internal signals to outer world * Using a debug core * Special case for ILA And for now come into our Newsletter and also follow us on LinkedIn. The post WFP017 – Debugging an FPGA appeared first on World of FPGA by David Kirchner.
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  WFP016 – FPGA Conference 2023 18.07.2023 20min

  It was time for a little trip again. This time I went to Munich to the three-day FPGA conference of PLC2 and the Vogel Verlag. Content of this Episode * 3 day FPGA Conference in Munich * A little insight * My attended lectures * Sessions on the first day * Linux Build Methodologies: PetaLinux vs. Yocto Flow * Coverage (aka Requirement Coverage) * Using property descriptions to formally verify FPGA design code * Synthesizing a Vivado Project on GitLab-CI and Deploying to an FPGA Board * Secure method of enabling multiple design in FPGA * Constraining Multiple Clock Domains * AMD-Xilinx: Dynamic Function Exchange with Device Tree Overlay * GDBServer in Hardware for VexRiscv Processing Systems * Next Generation of High-Speed Interfaces for Vision Applications * Sessions on the second day * Demystify a Vitis Embedded Acceleration Platform * MicroBlaze - A most flexible processor for FPGAs and MPSoCs * Self organizing administration tool to control FPGA designs * Fundamentals of Timing Analysis and Why No FPGA Design Can Do Without It * How to crash 100+ AWS FPGA instances and how to insert Trojans into bitstreams * Demonstration Setup for HashCache * Sessions on the third day * Do FPGA designers and hardware designers need to talk? A practical approach to shortening the project timeline * How your FPGA design decisions affect PCB board performance * Agilex SoC Architecture * Turning your FPGA into a fast multichannel ADC * PCIe, MIPI CSI-2, HDMI and DDR memory across platforms from an Open Source perspective * Constant On-Time (COT) Control for FPGA High-Current Power Supplies * Hardware attacks on FPGA: An overview of threats and security mechanisms Next FPGA conference is from July 2nd to 4th, 2024 And for now come into our Newsletter and also follow us on LinkedIn. The post WFP016 – FPGA Conference 2023 appeared first on World of FPGA by David Kirchner.